Well folks, it seems there’s no way around it. The 9500 series just doesn’t program well. A user must give up, implement retry, or cross their fingers and hope for that 1 in 520 chance that this time, all the bits will properly flash. Har!
So we printed out app note 67 and got to work building the retry sequence. After a bit of debugging and a bit of optimization, the tool was verified to program successfully by the OP of the problem. We now release it to you, fine readers, for your CPLD JTAG pleasures.
Fig 1 – V1.0 of the FT232 JTAG Tool. Now with Retry!
Some new additions (other than the retry code) are shown in red and blue. Red allows you to change the JTAG clock frequency by directly manipulating the FT232 clock divisor. Setting to 0, or checking “Max CLK” uses the FT232′s internal 3MHz clock directly (what we prefer). Or setting a divisor slows the JTAG bit banging to 3MHz/divisor. Try a number such as 78 for a 50kHz JTAG clock.
Shown in blue is the retry counter. We’ve heard from OP that even a “good” device will sometimes exceed the 32 retry counter, so feel free to set it to a higher number for those extra-high-quality devices that require more than 32 attempts.
Without further ado, here is the source code and precompiled executable for the new and improved bit bang JTAG programmer.