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Bit Bang JTAG Programming of Xilinx CPLD using FT232 – Homebrew SVF Player

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Connect Four (Well Six if You Count VDD and GND)

Now comes the easy part – just connect the boards and let it rip!  The JTAG interface of the CMOD board does NOT include a RESET pin, which seems to be typical.  So if you really munge things up in the state machine, remember there’s no hardware reset – so just unplug and replug USB.  By cutting the 5V USB supply to the FT232, you’ll also power down the CMOD.  You could alternately just disconnect the 3.3V supply to the CMOD, but it’s way easier to replug USB.

Below is the wiring used in the demo tool.  Remember, you have the freedom to switch around any of the JTAG lines to any of the FT232 bitbang pins if you don’t like this wiring below.  In these examples, we will pretend that the pinout is as it would be if the USB connecter were the IC notch.  We will not count the 4-pin header at the bottom, so pin 1 is top right below, and pin 18 is bottom right.  As it stands, the wiring diagram is as follows


Fig 3 – Wiring Diagram for Sparkfun FT232 as JTAG Programmer



Here’s that wiring diagram in text form for you colorblind hackers out there.

  1. CMOD VCC – FT232 +3.3V.  Either tie to the header we’ve shown here, or pin 5
  2. GND – FT232 GND.  Either tie to the header as we’ve shown here, or pin 16
  3. TCK – FT232 RI,  Pin  15
  4. TDO – FT232 DCD, Pin 18
  5. TDI – FT232 DSR, Pin 17
  6. TMS – FT232 RXD, Pin 14

If it’s the first time you’re running the tool with the CPLD connected, it’s best to single step.  That way, you can see each write/read of data and the device’s reply which is VERY useful for debugging.  After you have verified that the thing is working properly, go ahead and untick the Single Step checkbox and let it rip.

The software is more reliable when run from the .exe than it is in the VB6 debugger.  Specifically, single stepping the read data section – between the check for data in the buffer and the actual read of the buffer – can be unreliable if stepped.  No idea why, but that section of code is so bloody simple it must be something due to calling with VB6.  If you want to debug this section, then set a trap on the line AFTER the actual read of the buffer so the tool can query and read the buffer at a fairly quick pace.

Well folks, that’s pretty much it.  Please download and play around with the Openschemes_FT232_SVF_Player.  This download contains both source and executable, as well as a copy of the old version for reading and writing one byte at a time in case your interface is flaky and you can’t stand the RAW BIT BANG FURY!  Enjoy.

NOTE: The software in the link above is now outdated.

We will always update this section with a link to the newest version, and the release info on what the heck was changed.

Go to Openschemes FT232 SVF Player v0.11

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21 comments to Bit Bang JTAG Programming of Xilinx CPLD using FT232 – Homebrew SVF Player

  • haxor

    Link for the Openschemes_FT232_SVF_Player appears to be broken.

  • BSVi

    The software doesnt works. Firstly, it requires to have directory c:/temp created. I figured that out using procmon. Now, it doesnt detects my ft232r (No Interfaces yet.. in interfaces list). I’m sure that FT232R is connected and configured: I can use it with my terminal. I tryed both kinds of drivers: D2xx and VCP with no success. I’m runnung windows 7 OS. It would be great, If you figure out what is happening and fix the program. Thanks.

    • openschemes

      Good catch on the temp directory, a corrected version will be up soon. As far as the device description, what was the device description you had that did not contain FT232R? It would be dangerous to open it up to any interface, but easy to add another or a few more descriptions of common boards.

  • BSVi

    Oh, The problem was in device description. It has to contain “FT232R” string. Thank you!

  • bmx

    the nextstate array is wrong.

    0×0: Test-logic-reset 0 1
    0×1: Run-test/Idle 1 0
    0×2: Select-DR-scan 3 9

    should be

    0×0: Test-logic-reset 1 0
    0×1: Run-test/Idle 1 2
    0×2: Select-DR-scan 3 9

    Chears

  • pito

    Hi, does it work with FT232BM? Interface has been recognized, but none activity on selected signals..p.

  • pito

    ..FT232BM does support bitbang mode – ie see app note AN232BM-01 (..”The purpose of this mode was intended to be used to program FPGA devices..” y2002). Would be nice to get it working..There is a lot of modules around..p.

    • openschemes

      Good find – we stand corrected. It looks like the BM device contains a non-synchronous bit bang mode. With a little work, the tool could probably be adapted to use this FT232BM device, but the speed might be slower. Give it a try!

  • pito

    ..and the FT245BM (parallel FIFO bi-directional data transfer up to 1MB/sec).. also worth considering. And much easier to solder :) . Thanks.

  • jxm

    success! i wanted to tell you that with this instruction i was able to ‘tag my [device]. thank you!

  • Leon

    I have a question – does this software work with FT2232? Is FT2232 faster?

    • openschemes

      No, just FT232. There’s a million tools for jtag with 2232.

      • Shater

        For me, there wasn’t any broken piece of metal. It was a screw that was ssupoped to hold down the circuit board, just rolling around loose. All the other screws on that card were also loose. Tightened them and re-installed the loose one. Now maybe it won’t be the cause of any more unexpected freezes and resets. Thanks for the help in getting the case opened.Funny, just last week found a loose screw in our InFocus projector. That one let heat out of the lamp assembly, shutting the unit off!

  • Leon

    It works with XC9572XL!!! Thank you!!!!

  • CHIP konzol

    I will programing a Xc2c64a chip.
    I receive always this faliure
    here is a log
    “Opening c:\temp\falcon.svf
    > // Created using Xilinx Cse Software [Lab Tools - 13.2]
    > // Date: Mon Sep 26 14:40:05 2011
    > TRST OFF;
    No control over RST, ignoring
    > ENDIR IDLE;
    Set IR end state to IDLE
    > ENDDR IDLE;
    Set DR end state to IDLE
    > STATE RESET;
    > STATE IDLE;
    > FREQUENCY 1E6 HZ;
    My frequency is very low, ignoring this directive..
    > //Operation: Program -p 0 -e -v
    > TIR 0 ;
    0 leading IR bits OK
    > HIR 0 ;
    0 trailing IR bits OK
    > TDR 0 ;
    0 leading DR bits OK
    > HDR 0 ;
    0 trailing DR bits OK
    > TIR 0 ;
    0 leading IR bits OK
    > HIR 0 ;
    0 trailing IR bits OK
    > HDR 0 ;
    0 trailing DR bits OK
    > TDR 0 ;
    0 leading DR bits OK
    > //Loading device with ‘idcode’ instruction.
    > SIR 8 TDI (01) SMASK (ff) ;
    lNumBytes= 24
    Sent: 01
    Got: 00
    > SDR 32 TDI (00000000) SMASK (ffffffff) TDO (f6e5f093) MASK (0fff8fff) ;
    lNumBytes= 96
    Sent: 00000000
    Got: 00000000
    Masked Expectation: 06E58093, Masked Result: 00000000 Fail! Bailing out…

    Waht is the problem?
    Can you help me?

    • openschemes

      You are only receiving 0′s for any communication. Your wiring is not connected properly, or your pin selection is wrong.

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