Bit Bang JTAG Programming of Xilinx CPLD using FT232 – Homebrew SVF Player

A Steaming Pile of SVF

Although the XSVF file format would probably have been easier to write software for, the SVF file format in all it’s plain text glory is way easier for us human beings to understand.  So by following along in the log window as an SVF file is processed, you can get a better feel for the process and how it all fits together.  We even give a single step option in case you want to really investigate deeply or even hook up a scope or logic analyzer to watch what happens to the pins as each instruction or state change is processed.

Let’s first take a look at the SVF player software, and continue from there.

Fig 2 – Openschemes FT232 Bit Bang SVF Tool




Starting in the upper left, we have the FTDI section.  This is how you search out and select the FTDI interface you’d like to use.   Once your desired interface is found and opened, then we set the bit bang parameters directly below.  First, Clock Speed: Bit bang mode shifts data out using the baud clock, which is a divided-down master clock used to generate the standard RS232 baud rates.  Or, just tell the device to clock out our data with no divisor using the “Max CLK” checkbox.  Unless you’re having data problems, then Max CLK is where you want to be living.

Next, pinout.  You can use any of the available bit bang pins for any of the JTAG functions.  The pin selection shown as the default gives a convenient wiring scheme when using the Sparkfun FT232 Breakout Board.  The Make Magazine BUB Board looks like it is also a suitable device, as is any FT232 board capable of running at 3.3v.

Once your pins and clock rate are chosen, click Start Bitbang Mode to load the configuration to the FT232.  It is now ready for data transfer.  You can either connect the CPLD now, or just have it always connected – either way is fine.  You will want the FT232 board to supply +3.3v and GND to the CMOD (or other CPLD board), and at least for the CMOD we’ve found that the FT232 can supply enough juice to program it with no problems.  If you start getting into higher power devices such as FPGA’s, it’s better to let the FPGA’s power supply give 3.3v to that board, and only connect GND plus the 4 JTAG pins from the FT232.  More on wiring later.

The folder and file browsers in the upper right should be pretty self-explanatory.  Find an SVF file to play, and double click it.

Below the browse windows are the SVF commands.  The single step checkbox shows the upcoming SVF line in the log window, and then waits for the user to press the “Step” button to execute it.  Let’s say that again – when the command shows up, it is NOT YET executed and pressing the step button will ONLY THEN execute the line.  If you find yourself wanting to stop single stepping, press the break button and the execution will stop, and the file will be closed.  You will need to start execution again if you want to re-run after breaking.

Whether you choose single step or not, SVF execution is started by clicking the “Process SVF File”.  The file will be read in, and processing will begin.  You’re free to check and uncheck the single step option, if you decide you’d like to change modes.  If the tool is holding at a step point and the option is unticked, then it will begin to run full speed the next time the “Step” button is clicked.

All pretty self-explanatory.

Our standard disclaimer for software:  it’s crap, written hastily and probably containing bugs as well as hoards of unoptimized code.  We did improve it from a single byte write/read which took a really long time to flash the XC2C64A to a 4 byte, then a 64-byte chunk processing which improves the write time to about 2.5 minutes.  It was an optimization well worth doing but you may find fragments of the older revs still floating around.  Feel free to do any touchups you think are worthwhile and send the code back – we’d be happy to post your revision and props to you if you come up with something good.

You will notice that the time estimates are miscalculated – this is on purpose for some random case that came up too short.  It was easier to add a few milliseconds than to spend minutes looking for some stupid quirk of VB.

Please be assured that the tool is indeed working properly.  If you have read write fails, then untick  Max CLK and use a lower baud clock such as 57600.  If you still have issues, we will include an older version which only writes one byte at a time.  This one is more tolerant of poor wiring.  If even that fails, then your wiring must really be bad.  Please try to fix it.

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