Bit Bang JTAG Programming of Xilinx CPLD using FT232 – Homebrew SVF Player

Howdy Schemers,

We had to put the Digital Photoframe Projects on the shelf for a little while as we took care of some important business.  It seems that a popular PowerPC has some problems with a very thin reset pulse.  So thin that it’s often considered a reset glitch instead of a reset pulse.  Oh Noes!  You guys gotta take better care of your reset logic next time.  Another valuable lesson learned.

Now while we don’t care one bit about how this glitcher works or what it’s used for, it is certainly interesting that the CPLD has exploded in popularity and is programmed exclusively using JTAG.  Today’s lesson consists of the development of a bit-banged JTAG SVF player in order to program a device such as a CPLD.  It’s quite likely that the SVF player we develop today could program an FPGA or flash a micro or some other good stuff we haven’t thought of yet – SVF is a very powerful data format.  But at the moment, we’re going to stick to the task at hand – flash a bitstream to a CPLD using a homebrew JTAG interface.  Our interface will use the synchronous bit-bang mode of the FT232 chip, as has been previously described in: Bit Banging SPI on Arduino’s FT232 and Lattice CPLD programmer using FT232.   So let’s get to the program.

CPLD is Win

The CPLD board we’ll use for development today is the Digilent C-MOD board.  This board is based upon the Xilinx XC2C64A CPLD.   A CPLD (Complex Programmable Logic Device)  is a programmable logic chip, smaller and a bit more streamlined than an FPGA but still fairly closely related.  CPLD’s are mostly used as glue logic, or to implement smaller custom logic blocks in large designs.

CPLD’s are cool, and a worthwhile technology to have in hand because it’s REALLY nice to be able to implement a wee bit o’ custom logic without pinning out two hundred something FPGA pins.  In the reset pulse tester mentioned earlier, the CPLD watches a few lines for a start of a known routine and begins shooting little reset pulses after a variable delay.  If no problem is detected, the CPU is restarted with a little longer delay next time.  Overall, the delay is swept over a wide range to make sure your CPU is not susceptible to the reset glitch problem.

It seems that all over the world, concerned citizens are taking it upon themselves to ensure their CPU’s are not problematic.  We’re very proud to see so many non-g33k types take such an interest in supporting robust logic design, especially in the usually ignored categories of brownout and short pulse protection.  Kudos!  It seems that pretty much any board with an XC2C64A has been flying off the shelves, often into the hands of an average joe who simply isn’t interested in the headaches (read: FUN) associated with home bringup of programmable logic.

A common complaint is that folks are buying the CMOD or other compatible boards without having a programmer handy.  Darn!  The second most common (or related) complaint is that most PC’s manufactured after 1985 don’t have a parallel port.  That’s an unfortunate situation, having a fancy new toy and not being able to twiddle around with it.

We decided that it’s time to lower the barrier to entry on homebrew JTAG’ing Xilinx chips, and the best way to do that would be to take that stupid LPT wiggler and send it back to hell where it came from.  You want bit banging, you want USB convenience, and you want your programming jig to supply power to the target device.  Done, done, and done.  FT232.

Notice we said FT232, NOT FT2232.  That is +FT232 -FT2232 in googspeak and please don’t even ask if a 2232 version is in the works.  There’s a million projects that use the pre-packaged MPSSE mode of FT2232 to do all sorts of stuff way cooler than this.  This article is taking it back to the old school, and bringing a JTAG SVF player to the good old fashioned synchronous bit bang chip available on every arduino board on the planet.

What’s in store for you today?  You will learn how to traverse the standard JTAG TAP state machine in software, how to read and interpret the SVF file format, and how to churn data from your PC’s cozy USB port to the cold world of JTAG serial port using handcrafted square waves.
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