Turning a Top2005 EPROM Programmer into a Desktop Test Bench

Custom FPGA Logic

For the truly hardcore hackers out there, it is a simple task to take over the entire FPGA and have it run our own bistreams!   With this, you can implement custom logic to wiggle pins automatically, create precise timing delays between signals, and even implement fancy state machines to generate the tedious sequential signalling for things like StrataFlash or various ISP routines.   Yup, wrap it all up in verilog and fire your sequences when the 8051 writes register XX to value YY.   There’s tons of possibilities, so to make it simple we’ll start with a totally boring one – an open source implementation of ictest.bit that implements read/write and VPP control just like it’s proprietary cousin.

Since this FPGA is pretty old, you’ll be working with the Xilinx Spartan 4k ISE.   It does not come with a Verilog compiler, so it may not even be very useful at all except to compile the synthesized EDIF files to bitstream.   So far, we don’t know of any open-source methods of synthesizing for the SpartanXL so if you have one, leave us a comment!

UCF File

The first thing you’ll need is to define all the pin names in the FPGA in a   UCF (user constraint file) so you can refer to signals such as ZIF[23] instead of the actual FPGA p55.   That would be entirely maddening, and we couldn’t even begin to fathom it.   Lucky for you, we’ve written the UCF ourselves and GPL it here.   Consider the front matter disclosure, and this link the inclusion of the GPL license.

###########################################################################
# Top2005_XCS05.ucf - User Constraint File for the XCS05XL FPGA in Top2005
# Copyright 2010, Openschemes.com
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see gnu.org/licenses
###########################################################################
# The FPGA controls the logic-level signals to the Device Under Test (DUT),
# as well as the application of Programming Voltage (VPP).
# Additionally, the data bus between the 8051 and the FPGA is defined.
###########################################################################
#
# 24MHz Master Clock from PDIUSB12
# NET "MCLK" LOC = "P48";
#
# Serial Programming Signals - won't be used in code, for information only
#
#NET "nPROG" LOC = "P52";
#NET "nINIT" LOC = "P36";
#NET "CCLK" LOC = "P74";
#NET "DIN" LOC = "P72";
#
# 8051 Control/Data Bus
#
NET "ALE" LOC = "P99";
NET "nRD" LOC = "P35";
NET "nWR" LOC = "P21";
NET "D[0]" LOC = "P16";
NET "D[1]" LOC = "P15";
NET "D[2]" LOC = "P14";
NET "D[3]" LOC = "P13";
NET "D[4]" LOC = "P10";
NET "D[5]" LOC = "P9";
NET "D[6]" LOC = "P8";
NET "D[7]" LOC = "P7";
#
# Logic-Level Signals to the 40-pin ZIF Socket
# NOTE: ZIF01 is nearest the lever
# NOTE2: Any pins also driven to VCCx or VPP have
# series resistors placed on PCB to avoid damaging
# FPGA. Not great, but workable.
#
NET "ZIF[1]" LOC = "P98";
NET "ZIF[2]" LOC = "P96";
NET "ZIF[3]" LOC = "P94";
NET "ZIF[4]" LOC = "P92";
NET "ZIF[5]" LOC = "P90";
NET "ZIF[6]" LOC = "P86";
NET "ZIF[7]" LOC = "P84";
NET "ZIF[8]" LOC = "P82";
NET "ZIF[9]" LOC = "P80";
NET "ZIF[10]" LOC = "P78";
NET "ZIF[11]" LOC = "P70";
NET "ZIF[12]" LOC = "P68";
NET "ZIF[13]" LOC = "P66";
NET "ZIF[14]" LOC = "P62";
NET "ZIF[15]" LOC = "P60";
NET "ZIF[16]" LOC = "P58";
NET "ZIF[17]" LOC = "P56";
NET "ZIF[18]" LOC = "P54";
NET "ZIF[19]" LOC = "P47";
NET "ZIF[20]" LOC = "P45";
NET "ZIF[21]" LOC = "P46";
NET "ZIF[22]" LOC = "P53";
NET "ZIF[23]" LOC = "P55";
NET "ZIF[24]" LOC = "P57";
NET "ZIF[25]" LOC = "P59";
NET "ZIF[26]" LOC = "P61";
NET "ZIF[27]" LOC = "P65";
NET "ZIF[28]" LOC = "P67";
NET "ZIF[29]" LOC = "P69";
NET "ZIF[30]" LOC = "P71";
NET "ZIF[31]" LOC = "P79";
NET "ZIF[32]" LOC = "P81";
NET "ZIF[33]" LOC = "P83";
NET "ZIF[34]" LOC = "P85";
NET "ZIF[35]" LOC = "P87";
NET "ZIF[36]" LOC = "P91";
NET "ZIF[37]" LOC = "P93";
NET "ZIF[38]" LOC = "P95";
NET "ZIF[39]" LOC = "P97";
NET "ZIF[40]" LOC = "P3";
#
# VPP control pins - Active High. All signals apply the programmable VPP
# to the named pin except P40, which applies VPP-6v due to series Zener.
# Therefore VPP40 is named V6P40.
#
NET "nVPP1" LOC = "P43";
NET "nVPP5" LOC = "P42";
NET "nVPP7" LOC = "P41";
NET "nVPP9" LOC = "P40";
NET "nVPP10" LOC = "P39";
NET "nVPP11" LOC = "P34";
NET "nVPP12" LOC = "P33";
NET "nVPP14" LOC = "P2";
NET "nVPP15" LOC = "P32";
NET "nVPP20" LOC = "P31";
NET "nVPP26" LOC = "P4";
NET "nVPP28" LOC = "P30";
NET "nVPP29" LOC = "P29";
NET "nVPP30" LOC = "P28";
NET "nVPP31" LOC = "P27";
NET "nVPP34" LOC = "P44";
NET "nVPP35" LOC = "P5";
NET "nV6P40" LOC = "P6";
#
# Cheers,
# -oschemes

For the old-tymie Spartan 4k ISE, you’ll need to rename this UCF file to your project name, such as awesome.ucf if your project is named awesome and will generate the awesome.bit bitstream.   But once it’s included, you can go ahead and use the common names in your verilog.   For example:

assign ZIF[40:1] = 40′h0000000000;

Will drive all the pins of the ZIF socket low.   Much nicer than doing it individually with the FPGA pin names.   The first couple times you use the file, please check the pin map output file after mapping to make sure your pins are what you expect.   If you haven’t named the file properly, or if you’ve accidentally commented out some lines, the mapper will place whatever signal it wants onto whatever pin.   This usually results in the device hanging as one of the TOPBUS lines is invariably assigned as a ZIF output.   But in the very worst case it could apply VPP in places you don’t want and blow up your target IC.   Be conservative and don’t plug the IC until you’ve verified the static setup using a meter.


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