ZeroPlus Logic Cube – Review and Teardown

Once you’ve gotten the case off, you can see the LAP-C is a single-board device centered around a big old custom ASIC.   We’re not sure if it’s truly custom but since there’s no platform flash nearby it’s not a repackaged Xilinx.   Anyway, we trust ZP to be able to make an ASIC and have no need to decap this one, so this chip stays unmolested.

As we said before, we bought the cheapest one (LAPC 16032, 16 channel, 32k RAM) in hopes that we could hack it up.   Keep that in mind when reviewing the pix.

Fig 3 – Top of the LAP-C PCB

We’ll give a quick rundown of the operation.   USB comes in on a Genesys Logic GL-660 old-school USB->IEEE1284 controller, which must have been a legacy design as the 660 is all but dead as far as we can tell.   Here’s a GL-660USB Datasheet that really gives very little information.   We’re trying to determine if the 660 can write his own serial eeprom over USB, so if you know either way – plz contact us!

The GL660 interfaces directly to the ASIC, so let’s go there next.   It’s a ZeroPlus custom as we said before, marked ZP322MB-5.   Let’s inspect that again.   ZP 32 2MB -5.   Uh, looks like our chip is actually a 32 channel, 2MB RAM device.   Well that’s the top of the line analyzer there, buddy.   How’d we get that top-of-the-line chip in our crappy little 16032?

Economies of scale!   It’s way cheaper to make two of the same chip than one each of two types, so the standard practice is to make one full-featured IC and disable features for the peons who can’t afford those features.   It’s great for the manufacturer, and the loss due to nerds like us hacking in those missing features is still less than the cost of running two sets of wafers.   Now is that a bad thing to do?   Are we subverting something we shouldn’t?   What are the ethics of “hacking in” features.

We think of it like this: If you buy a Honda Civic, nobody would think twice about you ripping open the engine and installing a turbo or something.   Now you’ve added $5k to the value of the car for the few hundred bucks the turbo hardware would cost.   It’s the same thing here – we’re like mechanics for electronics.   We have the expertise, and enjoy the challenge so we will add, subtract, cut, patch, solder, and reflash whatever we can in order to soup up our toys..

So we know the main IC probably has the capability to do more than what the label says.   Let’s keep going.   The RAM chip just north of the ASIC is a Cypress CY7C1347G, which is a 4Mbit (128k x 36) pipelined synchronous ram (that means fast, and does stuff on clock edge only in order to be fast).   We make the guess that the width of 36 is probably used for 32 channels, so our installed RAM is 128k, not 32k!

That’s kind of weird – economies of scale don’t really apply to things like RAM because the “feature” is directly proportional to die size.   Cutting the ram in half requires just over half the silicon (fixed overhead for address decoder and sense amps, but half the cells) so the cost is nearly linear.   Cypress must have a SIGNIFICANT volume discount for buying multiple chips of one type   instead of fewer chips of multiple types.   In other words – Cypress is gouging the small customers, and it’s cheaper to buy 128k   and disable most of it than it is to buy a smaller RAM chip.   Our guess is due to the fixed package cost outweighing the silicon cost.

Good for us because we have a nice big chunk of memory on hand, and a master processor that can handle it.   Just in case you’re wondering – Replacing the 128k chip with a 2M chip is insanity without a hot air rework station, so don’t get greedy and start thinking that you can get the 322000 in a simple hack.   But a something-128 might be possible..  

All the way south on the PCB sits another ZeroPlus custom chip (DV4128B) and an LM348 quad 741 op-amp.   The ZP chip is a 3.3v Serial DAC, and with the op-amps is used to generate buffer voltages to adjust the trigger points for each of the 4 “ports”, where one port is 8 bits or 8 logic analyzer inputs. We really liked the clever design of the buffer, whereby adjusting the voltage at the top of a resistor divider sets up a fixed 1.67v trigger so a super cheap 74xx series buffer can be used as combination input level shifter and logic buffer.   More on that in a future article.

And last but not least, we have the 74LVT16245B 16-channel transceiver and it’s accompanying 16 R divider+RC arrays that is used in conjunction with the buffer voltage to translate various input levels to a fixed 3.3v logic level for the ASIC.   Again, this is a really elegant design and we’re glad to have been able to see it – Thanks, ZP!
Now you can take a look at the back of the board, which is mostly ground plane and routing except for 16 empty resistor padstacks for the unused channels that have inherent shorts to ground.   Guess it’s cheaper to draw a pcb trace than to pull the unused channels to GND with a resistor.   No argument there!

Fig 4 – Bottom of the LAP-C PCB

We’d better end the article here before we end up giving away too many secrets, but be sure to stay tuned for the next installment where we get buck nasty with the LAP-C.

As always, thanks for taking this little walk with us through a very cool device.   We hope your brains are already buzzing with ideas on possible hacks.

For those who’d like a higher-res photo of the front of the PCB, you can get it below or search around on the interwebs for some other really nice teardown pix.

Fig 5 – Higher Resolution PCB Pic

Cheers!

Openschemes