Advanced FT232 Bit Banging – Homebrew ISP CPLD Programmer


At this point you’ve just about mastered the Idle State – congratulations!   Now let’s complicate things a little by going on to state #2, the shift state.   This state is used for storing commands in the ISP mode.   State #2 uses a 5-bit shift register.   All shift registers wrap the output back to the SDO pin so if you keep writing the same thing over and over into SDI you will get it back on SDO.   This is sometimes useful if you want to make sure you got a good write.

The typical sequence is to transition from the idle state to the shift/command state and load in a command.   Then transition to execute state to run it and then back to the shift/command state.   The commands table below is taken from the ispLSI2032 datasheet.

Fig 7 – ispLSI Command Table


Some of these commands are essential, and some are extra.   We’ll take a moment to discuss the essential commands here.

• $01 – ADDSHFT - Loads 101 bits into the addr register.   102 clock execute state
• $02 – DATASHFT - Loads and sends 40 bits from the data register.   40 clock execute.
• $04 – ERALL - Erases the entire device, including UES.   1 clock execute with 200mS Flash erase wait time.
• $07 – PRGMH - Flash the data from data register into the HI memory bank.   Addr must be set.   1 clock execute with 90mS Flash wait time.
• $08 – PRGML - Flash the data into the LO memory bank at address . 1 clock execute with 90mS Flash wait time.
• $09 – PRGMSC - Program the security bit.   1 clock execute with 90mS Flash wait time.
• $0A – VER/LDH – Verify (Load for read out) the HI memory bank at address .   1 clock execute.
• $0B – VER/LDL – Verify (Load for read out) the LO memory bank.   1 clock execute.
• $0F – PRGUES – Program the UES Scratchpad from the 40-bit data in data register. 1 clock execute with 90mS Flash wait time.
• $11 – VERUES – Verify (Load for read out) the 40 bit UES data.   1 clock execute.


The reason we discuss the number of clocks to execute is because the datasheet and programming manual are very confusing with regards to the proper sequences.   In some places it is discussed correctly and in other places it is discussed using incorrect or ambiguous wording.   To avoid confusion, we will discuss the proper sequence for flashing one data register ( a high register) in it’s entirety.

1. Reset part, or latch HL to get into idle state
2. Latch HH to get into shift/command state
3. Send 5 bit command $01 – ADDSHFT
4. Latch HH to go to execute state
5. Send 102 bit Address data.   Since MODE is low during transfer, this is a combination transfer/execute.   Address will stay at this value until you shift a new addr in.
6. Latch HH to return to shift/command state
7. Send 5 bit command $02 – DATASHFT
8. Latch HH to go to execute state
9. Send 40 bit fuse data – Again a combination transfer/execute.   Now the fuse data is stored in the data register.
10. Latch HH to go back to shift/command state
11. Send 5 bit command $0A – PRGMH
12. Latch HH to go to execute state
13. Latch LX, and wait 90mS to execute the flash.
14. Latch HH to go back to shift/command state.
15. Prepare the data for the low register, and loop to step 7 to flash it.

It may seem complicated, but it’s actually pretty strightforward.   You bounce back and forth between the shift and execute states and read/write where appropriate.   Keep a copy of the state diagram handy to use for reference.

You’ve already seen the HL scope shot so here’s a pic of a 5-bit command shift of $02 – DATASHFT.   We’re ignoring data out in this case (CH4, Green) but if you look closely you can see the last command shifting back out.   In this case it must have been $11, VERUES.

Fig 8 – Scope shot of a command shift of $02 – DATASHFT command


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