Advanced FT232 Bit Banging – Homebrew ISP CPLD Programmer


Let’s take a moment to look at the mechanics of the 2032′s ISP mode.   We enter ISP mode by bringing nISPEN low.   After that, we use the SPI port to change states and to transfer data in and out.   To change states, we set MODE and SDI to miscellaneous codes and strobe the CLK line high, then low.   Both state changes and data shifting happens on the rising edge of CLK.   Here’s the state diagram of the ISP mode from the datasheet.

Fig 3 – ispLSI State Diagram


Each of the large circles is a state (or mode).   Each state has different functions for reading, writing, programming, etc.   We transfer between states by setting MODE, SDI to the levels shown on the transitions (arrows) and strobing one CLK.   While we’re in a state, we can transfer commands or data as if the device was a simple shift register.

If you don’t know what state you’re in, setting MODE,SDI to High, Low (here HL) will always get you back to the idle state.   Let’s take a look at the HL Sequence.   First, we set MODE high and SDI low, then we strobe the clock.

Let’s take a look at the sequence on the scope.   The traces are:

• CH1 (Yellow) – SCK
• CH2 (Blue) – MODE
• CH3 (Purple) – SDI (Programmer’s data out, MOSI)
• CH4 (Green) – SDO (Programmer’s data in, MISO)   Here, we don’t care about SDO.




Fig 4 – Executing the HL Sequence to get into the Idle State


In the idle state, the only thing you can do is read out the device ID.   That takes two steps.

1) Set MODE, SDI to LX and strobe CLK. X means don’t care so SDI can either be high or low.   For brevity, we will call it LX but we will implement as LL.   Strobing LX is the “execute command” sequence.   When executed in the idle state, this loads an 8-bit shift register with the device ID.

2)   Shift out the Device ID Data.   This is done by sending 8 clocks, and reading out the data that appears on SDO.   It doesn’t matter what data you send to the device, so we usually send 0′s.

Fig 5 – LL Sequence                               Fig 6 – Reading ID


In figure 4, you can see that MODE and SDI (Blue, Purple) are both low when the clock rises.   In figure 5, the first bit of data is already available so we read it on the rising edge of clock.   On the falling edge, the CPLD advances the shift register and the next bit becomes available.   The data is LSB first: 10101000.   Reversing it gives 0001 0101, or $15, the proper device ID for ispLSI2032.   Cool – it’s alive!


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